this method is so easy all of you can do it so simple
first you need white ip but:
You need ARP protocol to perform physical address resolution isp, ARM TrustZone technology and ARM Jazelle technology, and support ARM Intelligent Energy Manager (IEM) technology. They implement a Virtual Memory System architecture, and have AMBA 3 AXI interfaces. They support the ARM instruction set and the original Thumb instruction set. The ARM1176JZF-S processor has a floating point coprocessor. AMBA 3 AXI interfaces. They support the ARM and Thumb instruction sets, with the Thumb-2 extensions. The ARM1156T2F-S processor has a floating point coprocessor. They support the ARM instruction set and the original Thumb instruction set. The ARM1136JF-S processor has a floating point coprocessor. normal execution running 16-bit and 32-bit halfword aligned Thumb instructions. region is Execute Never (XN), and so instruction fetches are prohibited. An MPU, if present, cannot change this.for vendor system peripherals. This memory region is XN, and so instruction fetches are prohibited. An MPU, if present, cannot change this.
HOPE YOU lIKE THIS METHOD
first you need white ip but:
You need ARP protocol to perform physical address resolution isp, ARM TrustZone technology and ARM Jazelle technology, and support ARM Intelligent Energy Manager (IEM) technology. They implement a Virtual Memory System architecture, and have AMBA 3 AXI interfaces. They support the ARM instruction set and the original Thumb instruction set. The ARM1176JZF-S processor has a floating point coprocessor. AMBA 3 AXI interfaces. They support the ARM and Thumb instruction sets, with the Thumb-2 extensions. The ARM1156T2F-S processor has a floating point coprocessor. They support the ARM instruction set and the original Thumb instruction set. The ARM1136JF-S processor has a floating point coprocessor. normal execution running 16-bit and 32-bit halfword aligned Thumb instructions. region is Execute Never (XN), and so instruction fetches are prohibited. An MPU, if present, cannot change this.for vendor system peripherals. This memory region is XN, and so instruction fetches are prohibited. An MPU, if present, cannot change this.
HOPE YOU lIKE THIS METHOD