Any computer / electrical engineers around here?

[bk071]

I know its a LONG shot but hell I'll give it a try... I need help with an assignment. Let me know if you can help. I'll even pay if you don't feel like doing it for free.

Here's what I need help with:

Let me know if it makes any sense.

 

[Sherb]

Q1: If a branch outcome is to be determined earlier, then the branch must be able to read its operand equally early. Branch direction is controlled by a register value that may either be loaded or computed. If the branch register value comparison is performed in the EX stage, then forwarding can deliver a computed value produced by the immediately preceding instruction if that instruction needs only one cycle in EX. There is no data hazard stall for this case. Forwarding can deliver a loaded value without a data hazard stall if the load can perform memory access in a single cycle and if at least one instruction separates it from the branch.

If now the branch compare is done in the ID stage, the two forwarding cases just discussed will each result in one data hazard stall cycle because the branch will need its operand one cycle before it exists in the pipeline. Often, instructions can be scheduled so that there are more instructions between the one producing the value and the dependent branch. With enough separation there is no data hazard stall.

So, resolving branches early reduces the control hazard stalls in a pipeline. However, without a sucient combination of forwarding and scheduling, the savings in control hazard stalls will be offset by an increase in data hazard stalls.

EDIT: Just a heads up, that source is Google. Tread lightly.

 

[bk071]

Q1: If a branch outcome is to be determined earlier, then the branch must be able to read its operand equally early. Branch direction is controlled by a register value that may either be loaded or computed. If the branch register value comparison is performed in the EX stage, then forwarding can deliver a computed value produced by the immediately preceding instruction if that instruction needs only one cycle in EX. There is no data hazard stall for this case. Forwarding can deliver a loaded value without a data hazard stall if the load can perform memory access in a single cycle and if at least one instruction separates it from the branch.

If now the branch compare is done in the ID stage, the two forwarding cases just discussed will each result in one data hazard stall cycle because the branch will need its operand one cycle before it exists in the pipeline. Often, instructions can be scheduled so that there are more instructions between the one producing the value and the dependent branch. With enough separation there is no data hazard stall.


So, resolving branches early reduces the control hazard stalls in a pipeline. However, without a sucient combination of forwarding and scheduling, the savings in control hazard stalls will be offset by an increase in data hazard stalls.

Awesome. Thanks man. Any idea about the other two?

 

[davids355]

I would have happily helped you out for free but this has gone way over my head

 

[bk071]

I would have happily helped you out for free but this has gone way over my head

Thanks David, I know you would have.
Its a bit over my head too, that's why I asked for help from my BHW bros xD

 

[sockpuppet]

here my try on Q2:

got that image from google the red ones are my changes, as you can see on my awesome multiplexer

my necessary assumptions:
-the ALU has a comparison op witch sets neg and zero flag
-the instruction uses the r format

controls
RegDst: 1
Branch: X
MemRead: X
MemtoReg: X
ALUOp: code for compare, don't know
MemWrite: X
ALUSrc: 0
RegWrite: 1
My Additional Control Flag: 0 (needs to be set 1 for all other stuff)

what this does
-op2 == register1
-op3 == register2
-set the ALU to compare, which sets neg and zero flag
-the third red (from left to right) multiplexer selects the op2 or op3 based on the neg flag
-the second one selects either 0 or the result from the third based on the zero flag
-the first one selects between the compare result and the result from the Data memory

and that will work with all the other formats as long as you set the red control flag to 1


Q3:

 F | ID | EX | MEM | WB
 1
 2   1 
 3   2     1
 4   3     2    1
 5   4     3    2     1

instruction 1 is on write back: write R1
instruction 4 is on instruction decode/fetch register: read R11, R12

 

[Leith]

Let me know if it makes any sense.

 

[SeoWrecker]

here my try on Q2:

got that image from google the red ones are my changes, as you can see on my awesome multiplexer

my necessary assumptions:
-the ALU has a comparison op witch sets neg and zero flag
-the instruction uses the r format

controls
RegDst: 1
Branch: X
MemRead: X
MemtoReg: X
ALUOp: code for compare, don't know
MemWrite: X
ALUSrc: 0
RegWrite: 1
My Additional Control Flag: 0 (needs to be set 1 for all other stuff)

what this does
-op2 == register1
-op3 == register2
-set the ALU to compare, which sets neg and zero flag
-the third red (from left to right) multiplexer selects the op2 or op3 based on the neg flag
-the second one selects either 0 or the result from the third based on the zero flag
-the first one selects between the compare result and the result from the Data memory

and that will work with all the other formats as long as you set the red control flag to 1


Q3:

 F | ID | EX | MEM | WB
 1
 2   1 
 3   2     1
 4   3     2    1
 5   4     3    2     1

instruction 1 is on write back: write R1
instruction 4 is on instruction decode/fetch register: read R11, R12

Exactly !
you beat me to it by like 10 seconds.

 

[bk071]

here my try on Q2:

got that image from google the red ones are my changes, as you can see on my awesome multiplexer

my necessary assumptions:
-the ALU has a comparison op witch sets neg and zero flag
-the instruction uses the r format

controls
RegDst: 1
Branch: X
MemRead: X
MemtoReg: X
ALUOp: code for compare, don't know
MemWrite: X
ALUSrc: 0
RegWrite: 1
My Additional Control Flag: 0 (needs to be set 1 for all other stuff)

what this does
-op2 == register1
-op3 == register2
-set the ALU to compare, which sets neg and zero flag
-the third red (from left to right) multiplexer selects the op2 or op3 based on the neg flag
-the second one selects either 0 or the result from the third based on the zero flag
-the first one selects between the compare result and the result from the Data memory

and that will work with all the other formats as long as you set the red control flag to 1


Q3:

 F | ID | EX | MEM | WB
 1
 2   1 
 3   2     1
 4   3     2    1
 5   4     3    2     1

instruction 1 is on write back: write R1
instruction 4 is on instruction decode/fetch register: read R11, R12

You're a freaking star, mate.
I'm software oriented guy so pretty much a noob when it comes to hardware side of things.
Oh and awesome MUXes by the way.

Thanks again for the help

 

[seogiantking]

It's way too high for me.